Affan Iqbal
Open to work — Design Verification / RTL / Digital Design

Affan
Iqbal

Design Verification Engineer — RTL Design & Functional Verification

I write RTL in Verilog and SystemVerilog, and I verify it in simulation before it reaches hardware. My work sits between computer architecture and the testbenches that prove a design actually does what it's supposed to.

LOC Dallas–Fort Worth, TX PROGRAM M.S. Computer Systems Engineering — Univ. of Houston, May 2026 GPA 3.8 / 4.0
LinkedIn ↗ GitHub ↗ Email
CH1 — CLK CH2 — DATA 1.8V / DIV
01 — About

About

I'm an engineer focused on design verification and digital design, currently finishing an M.S. in Computer Systems Engineering at the University of Houston. I build testbenches and run functional verification in ModelSim, then take designs through synthesis in Intel Quartus Prime and onto an FPGA.

I also work below RTL. With a partner, I designed a transistor-level 4×4 DRAM array in 180nm CMOS using LTSpice — row and column decoders, sense amplifiers, and CMOS flip-flop row buffers, with FSM-based control logic sequencing read, write-back, and refresh.

My graduate coursework centers on computer architecture: cache design and coherency protocols, instruction-level parallelism and pipelining, FSM design, and digital logic design. That background is what I lean on when working out what a design actually needs to be tested for.

I came to verification from a software background — I still work in Python, C++, and Java, with a foundation in data structures, algorithms, and object-oriented programming. I'm looking for Design Verification, RTL Design, and Digital Design Engineer roles.

Projects

4 selected
02 — Projects
01Feb – Apr 2026
University of Houston
ECE 6370

ROM-Based Password Access Control

FSM-driven password authentication written in synchronous Verilog RTL, with the password held in ROM and an LFSR-based module driving system timing. Verified state transitions, ROM reads, and timer behavior against structured testbenches in ModelSim before synthesizing and testing the design on a DE0-CV FPGA in Intel Quartus Prime.

VerilogFSMModelSim QuartusDE0-CVRTL Design
github.com/affaniqbal9/ROM-Access-Control ↗
02Sep – Dec 2025
Two-person team

4×4 DRAM Array — VLSI

Transistor-level 4×4 DRAM array designed in 180nm CMOS: 1T memory cells, 2-to-4 row and column decoders, sense amplifiers, and CMOS D flip-flop row buffers. FSM-based control logic sequences destructive read, automatic write-back, and refresh. Simulated end-to-end in LTSpice at 1.8V.

LTSpiceCMOSVLSI Semiconductor MemoryFSM
github.com/affaniqbal9/VLSI-DRAM-Project ↗
03Oct 2023 – Jun 2024
Bachelor's project

Algorithm Visualizer

Full-stack Django application visualizing 9 classic algorithms — 5 sorting, 2 searching, and BFS/DFS graph traversal — each implemented from scratch with step-by-step animations.

PythonDjangoJavaScript HTML/CSSSQLiteData Structures
github.com/affaniqbal9/Algorithm-Visualizer ↗
04Mar – Aug 2023
Bachelor's project

IoT Contactless Smart Doorbell

Embedded systems project building a contactless doorbell around a Raspberry Pi and an ESP8266, with control logic and firmware written in C++ and Python.

Raspberry PiESP8266IoT Embedded SystemsC++Python
03 — Skills

Skills

Verification & RTL
VerilogSystemVerilogModelSim Intel Quartus PrimeFunctional Verification Testbench DesignRTL DesignFSM Design Digital Logic
Computer Architecture & Circuits
Cache Design & CoherencyInstruction-Level Parallelism PipeliningVLSICMOSLTSpice
Languages
PythonC++Java JavaScriptSQLHTML/CSS
Software & Tools
DjangoAndroid SDKFirebase SQLiteGit
04 — Education

Education

M.S., Computer and Systems Engineering

University of Houston
Relevant coursework: Advanced Computer Architecture · Advanced Topics in Computer Architecture · Advanced Imaging Techniques
Aug 2024 – May 2026
GPA 3.8 / 4.0

B.E., Information Technology

Osmania University — MVSR Engineering College
2020 – 2024
05 — Certifications

Certifications

06 — Contact

Let's talk verification.

If you're hiring for Design Verification, RTL Design, or Digital Design roles — or just want to talk architecture or testbench design — I'd like to hear from you.

iqbalaffan56@gmail.com LinkedIn ↗ GitHub ↗